The performance and power of conventional microprocessors are limited by RC characteristics of long on-chip interconnects. The RC characteristics cause the delay of signals that are transmitted over the interconnects. Of these characteristics, coupling capacitance (Cc) between neighboring signal lines contributes approximately 50% of total line capacitance, even in the case of copper lines.
The effective coupling capacitance of a signal line is equal to Cc multiplied by a Coupling Capacitance Multiplier (CCM). The CCM for a particular signal line is dependent upon the relative directions of signal transitions within the particular signal line and within a neighboring line. If the particular signal line carries a signal transition from a first signal level to a second signal level, CCM for the signal line is 1 if the neighboring line does not carry a signal transition, 0 if the neighboring line carries a signal transition from the first signal level to the second signal level, and 2 if the neighboring line carries a signal transition from the second signal level to the first signal level.
FIG. 1 illustrates a conventional static bus architecture for the purpose of explaining capacitive effects that result from adjacent signal transitions on neighboring signal lines. Bus 1 includes signal paths 10, 20 and 30. Signal path 10 comprises driver flip-flop 11, receiver flip-flop 12 and repeaters 13 through 16 connected serially therebetween. Repeaters 13 through 16 are intended to reduce signal delays caused by path 10 by creating a linear relationship between the length of signal path 10 and the signal delay associated therewith. Moreover, repeaters 13 through 16 are inverters that convert a received signal of a first signal level to an output signal of a second signal level. Signal paths 20 and 30 are constructed similarly to signal path 10.
FIG. 2 is a timing diagram illustrating signals on signal paths 10, 20 and 30 of bus 1. The diagram assumes that the bit values xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d are to be transmitted over signal paths 10, 20 and 30, respectively. As shown, each of these values initially undergoes a transition between time t1 and t2 due to a respective one of repeaters 13, 23 and 33. In particular, repeater 23 converts the signal on path 20 from a low signal level to a high signal level and repeaters 13 and 33 convert the signals on paths 10 and 30 from a high signal level to a low signal level. Accordingly, CCM of signal path 20 relative to signal path 10 is 2, and relative to signal path 30 is also 2. In addition, transitions occurring between times t3 and t4, t5 and t6, and t7 and t8 each result in a CCM of 2 for signal path 20 relative to signal path 10, and a CCM of 2 for signal path 20 relative to signal path 30. The resulting impact on worst-case delay, energy and peak supply current often renders the architecture of bus 1 unsuitable.
The delay of a bus can be improved by avoiding the worst-case situation of a CCM equal to 2. One approach uses a dynamic bus, in which bus segments pre-charge during one clock phase and conditionally evaluate in the next phase. Such a dynamic bus provides a worst-case CCM of 1 because all bus segments pre-charge and evaluate in a same direction. However, dynamic buses require additional clock routing and suffer from increased switching activity relative to static buses. Another approach uses a pulse generator to send a pulse along a static bus for each input data transition. This latter approach requires additional overhead of a pulse generator and a decoder to decode the pulses.